The present invention relates to a flat panel display device, particularly to a thin display such as an organic EL panel and a liquid-crystal panel.
An active matrix organic EL display is known as an example of a thin display. A representative configuration of a panel unit of the active matrix EL display is shown in FIG. 1. This panel unit has a configuration in which a color filter substrate 12 is adhesively attached to a circuit board (TFT substrate) 11 having light-emitting elements (for example, organic EL elements) or pixel circuits formed thereof. The reference numeral 13 in the figure denotes an outer peripheral seal region.
FIG. 2A is a schematic diagram illustrating the wiring configuration of the circuit board 11. A plurality of power source lines 21 arranged parallel to each other in the vertical direction and a power source bus 22 connected to these power source lines 21 and led out to an anode power source terminal (GND terminal) 23 are present on the circuit board 11. A plurality of pixel circuits 24 are connected to each power source line 21.
In such a circuit board 11, a planarizing resin layer is usually provided and concavities and convexities produced by TFT (Thin Film Transistors) or the like of the pixel circuits 24 are planarized by the planarizing resin layer. Contact holes 27 for connecting the pixel circuits 24 and the light-emitting elements are provided in the planarizing resin layer.
Each pixel circuit 24 is connected to a data control circuit 17 via a data signal line (course signal line) 25 and connected to a gate control circuit 18 via a scan signal line (gate signal line) 26.
FIG. 2B is a schematic diagram illustrating only the wiring to a power source. As shown in the figure, wirings extending in one direction, rather than solid- or mesh-like wirings, are often used for wiring the power source lines 21. With such wirings, the transverse sectional area of the power source lines 21 related to the data signal lines 25 and scan signal lines 26 shown in FIG. 2A is reduced and capacitance between wirings is decreased. Therefore, signal delay caused by the capacitance between the wirings can be inhibited. Yet another advantage is that when the pixels are small, the surface area of a transistor in the pixel surface 24 can be increased, although slightly. The reference numeral 16 denotes an integrated control circuit (a data control circuit 17 and a gate control circuit 18).
A representative configuration of the pixel circuit 24 is shown in FIG. 3. This pixel circuit 24 is used for driving a liquid crystal or an organic EL element and provided with a TFT 32 that is a drive transistor and a TFT 33 that is a control transistor. The source and gate of the TFT 33 are connected to the data signal line 25 and the scan signal line 26, respectively.
In this pixel circuit 24, an electrode to which a voltage VDD is applied (an upper transparent electrode to which all the pixel circuits 24 are commonly connected) is an anode. Ground or GND, to which the source of the TFT 32 is connected, is a cathode. The reference numeral 34 denotes a capacitor.
The structure of a pixel portion provided at the panel shown in FIG. 1 will be described below. FIG. 4A is a plan view of the pixel portion. FIG. 4B and FIG. 4C are cross-sectional views along the A-A line and B-B line in FIG. 4A.
As shown in FIGS. 4B and 4C, a planarizing resin layer 40 is present on a glass substrate 37. As mentioned hereinabove, this planarizing resin layer 40 is provided to planarize the concavities and convexities generated by the TFTs or the like of the pixel circuits 24. The planarizing resin layer 40 is covered, if necessary, with an inorganic passivation film.
A reflective electrode 42 is disposed, via a base layer 41 serving to improve adhesion, on the planarizing resin layer 40, and an insulating film 43 having an opening is formed at the light-emitting portion herein. Then, a plurality of organic film portions 44 are vapor deposited, and a transparent electrode layer 45 is formed thereupon. The transparent electrode layer 45 referred to herein is called an upper transparent electrode layer. A transparent layer composed of an oxide such as IZO or ITO or a half-mirror-shaped metal film with a thickness of from several nanometers to ten odd nanometers can be provided as the upper transparent electrode layer 45.
FIG. 5A is a schematic diagram of a wiring relating only to the transparent electrode layer 45. Furthermore, FIG. 5B is a cross-sectional view along the C-C line in FIG. 5A. Because the transparent electrode layer 45 is a common electrode for all the pixels, the layer has a solid wiring structure (surface wiring structure), as shown by the reference numeral 53 in FIG. 5A. The transparent electrode layer 45 is connected at the outer peripheral portion of the panel to a power source bus 51 that is different from the above-described one and led out to a terminal 52. The entire surface of the transparent electrode layer 45 is covered with a barrier layer 46.
The configuration described above is on the side of the circuit substrate 11 shown in FIG. 1.
Meanwhile, a black matrix 47, a color filter 48, and optionally a bank partition wall 39 or a color conversion layer 49 are formed on the glass substrate 38 on the side of the color filter substrate 12 shown in FIG. 1. It goes without saying that there are also systems using no bank partition wall 39 or color conversion layer 49. Furthermore, if necessary, a spacer 50 can be also provided.
The circuit board 11 and color filter substrate 12 are adhesively joined together with alignment ensuring the appropriate formation of pixels. A gap layer 54 is typically configured by a solid material such as an adhesive, but it is also sometimes configured by a liquid or gas.
In the circuit board 11 such as shown in FIG. 2A and FIG. 2B, the wiring resistance cannot be ignored because thick-film wiring such as a printed circuit board is difficult. Therefore, in the case of a display using current-driven self-emission elements, such as an organic EL panel, the current flowing in the power source lines 21 is higher than that in a display using liquid crystals or the like. As a result, voltage drop (rise) at the power source lines 21 or power source bus 22 increases.
The aforementioned voltage drop (rise) not only increases power consumption, but also causes in-screen distribution of voltage applied to light-emitting elements, thereby causing brightness unevenness.
Furthermore, when the pixel circuit 24 has a configuration such as shown in FIG. 3, in particular, when the GND potential rises, a gate control voltage of the TFT 32 fluctuates. As a result, even a slight in-plane distribution of potential causes a very large brightness unevenness. In this case, a very small number of pixels located close to the power source terminal 23 (see FIG. 2A and FIG. 2B), and having applied thereto a regular GND potential or a potential close thereto, become very bright. If such a state is allowed to stay and the average brightness of the entire panel is set, it can even lead to screen burning.
Accordingly, Japanese patent 3770368 suggests a technique for inhibiting such a phenomenon. The technique described in this reference involves electrically connecting a second conductor layer via contact holes to a power source line that is a first conductor layer, thereby forming a power source line path with a large cross section area combining those of the first conductor layer and the second conductor layer, that is, with a low electric resistance.
However, the technique described in Japanese patent 3770368 requires the addition of contact holes and the second conductive layer and, therefore, rises the production cost and increases the size.